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[VHDL-FPGA-VerilogALAW_LINEAR_CONVERTER

Description: This a HDL implementation of G711 A-LAW codec. It converts LINEAR to ALAW and vice versa. -This is a HDL implementation of G711 A-LAW codec. It converts LINEAR to ALAW and vice versa.
Platform: | Size: 3072 | Author: Christian | Hits:

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